In electronics, an analog-to-digital converter (ADC), commonly referred to as ADC or A-to-D or A/D, is a device for converting an input analog voltage (or current) to a digital number proportional to the magnitude of the voltage (or current) or a digital code. Multi-level ADCs can be useful in high-speed applications, for example for converting an input analog signal into a digital signal prior to digital signal processing. There are various configurations of ADCs, but two main types are successive-approximation ADCs and delta sigma ADCs. A successive approximation ADC uses a comparator to reject ranges of voltages, eventually settling on a final voltage range. Successive approximation works by constantly comparing the input voltage to the output of an internal DAC, which is fed by the current value of the approximation, until the best approximation is achieved. At each step in this process, a binary value of the approximation is stored in a successive approximation register (SAR). The SAR uses a reference voltage (which is the largest signal the ADC is to convert) for comparisons. SAR type ADCs may include single slope converters, dual slope converters, and incremental converters (which can also be considered a continuous time delta sigma modulator (DSM)). The conventional delta sigma ADCs incorporate a noise-shaping technique that allows noise, introduced by the ADC (sometimes referred to as a quantizer), to be moved to frequencies that can be filtered out of the digital output. The delta sigma ADC uses a feedback DAC to feedback the error signal in the quantized output.
The resolution of the ADC indicates the number of discrete values the ADC can produce over the range of analog values. The values are usually stored electronically in binary form, so the resolution is usually expressed in bits. In consequence, the number of discrete values available, or “levels”, is usually a power of two. For example, an ADC with a resolution of 8 bits can encode an analog input to one in 256 different levels, since 28=256. The values can represent the ranges from 0 to 255 (i.e. unsigned integer). To increase the effective resolution for an ADC, multiple samples can be filtered to produce more resolution, such as illustrated in the ADC circuit 100 of FIG. 1A. For every N samples the noise is reduced by √N. Another conventional method is to use a feedback DAC to build a delta sigma modulator, such as illustrated in the delta sigma modulator 150 of FIG. 1B. Conventional delta sigma ADCs (D-S ADCs) typically include a difference (delta) circuit, an integrator or accumulator (sigma) circuit, and a quantization (modulation) circuit, including an ADC and a feedback DAC, such as illustrated in the circuit 150 of FIG. 1B. Using the proper filter for N samples, the noise can be reduced by N3/2. Both of these techniques are well understood and commonly used in industry.
Averaging signals only gives you ½ bit increase in resolution for every doubling of samples. This works out to be one extra bit of resolution for each ¼ reduction in the sample rate. For example, as shown in FIG. 1, increasing the resolution by 4 bits (16) requires 256 samples (162), effectively reducing the data rate by that amount. A 1 Ms/s at 12 bits becomes 16 bits at 3.9 ks/s. Clearly the sample rate has been seriously affected. In a delta sigma configuration, the feedback DAC allows the noise to be shaped using less extreme filtering. Averaging N values results in a noise improvement of
      1                  N        3              .This works out to be 3 extra bits of resolution for every ¼ reduction in the sample rate. For example, a 12-bit ADC with a feedback DAC only requires 8, 12-bit samples to produce a 16-bits resolution. For the same 1 Ms/s ADC the new rate is @ 125 ks/s.
The disadvantage of conventional multi-bit delta sigma modulators, such as illustrated in FIG. 1B, is that performance is limited by the mismatch and nonlinearity of the ADC and the feedback DAC. For ideal quantization in the DSM, the results are shown in the equation (1) below:DAC(ADC(νin))=νin+eq,  (1)where eq represents the quantization error. Quantization error is due to the finite resolution of the ADC, and is an unavoidable imperfection in all types of ADC. The quantization error may be measured in terms of the least significant bit (LSB). Equation (2) shows the relationship between the output and the input in an ideal DSM.Vout=Vin+eq(1−z−1)  (2)However, when the ADC and DAC of the circuit are mismatched, the results from the quantization mismatch are shown in the following equation (3):DAC′(ADC(νin))=νin+ε(νin)+eq,  (3)where eq represents the quantization error and e represents the noise introduced from the mismatch. Equation (4) shows the relationship between the output and the input in a mismatched DSM.Vout=Vin+ε(Vin)+eq(1−z−1),  (4)Thus, mismatches in the ADC/DACs results in distortion, limiting the resolution enhancement because the distortion adds noise to the output signal and reduces the overall signal to noise ratio.